This invention relates generally to floating gate semiconductor memories such as electrically erasable programmable read-only memories (EEPROM) and flash EEPROM, and specifically to circuits and techniques for reading or sensing their memory states.
EEPROM and electrically programmable read-only memory (EPROM) are typically used in digital circuits for non-volatile storage of data or program. They can be erased and have new data written or xe2x80x9cprogrammedxe2x80x9d into their memory cells.
An EPROM utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over but insulated from a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate, but also insulated therefrom. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage (threshold) that must be applied to the control gate before the transistor is turned xe2x80x9conxe2x80x9d to permit conduction between its source and drain regions is controlled by the level of charge on the floating gate.
The floating gate can hold a range of charge and therefore an EPROM memory cell can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window, delimited by the minimum and maximum threshold levels of the device, depends on the device""s characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level within the window may, in principle, be used to designate a definite memory state of the cell.
In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding threshold voltage may be detected, or equivalently, a corresponding conduction current with respect to a reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.
For EPROM memory, the transistor serving as a memory cell is typically programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate. The memory states are erasable by removing the charge on the floating gate by ultraviolet radiation.
An electrically erasable and programmable read-only memory (EEPROM) has a similar structure but additionally provides a mechanism for removing charge from its floating gate upon application of proper voltages.
An array of such EEPROM cells is referred to as a xe2x80x9cFlashxe2x80x9d EEPROM array when an entire array of cells, or significant group of cells of the array, is erased together (i.e., in a flash). Once erased, the group of cells can then be reprogrammed.
FIG. 1 illustrates schematically a typical array of non-volatile memory cells 10, such as EPROM, EEPROM or flash EEPROM, accessible by a series of bit lines 20, 22, 24, . . . , and word lines 30, 32, . . . Each memory cell 40 has a source 43, a drain 44, a control gate 46 and a floating gate 48.
A specific cell in a two-dimensional array of EPROM or EEPROM cells is addressed for reading typically by application of a source-drain voltage to a pair of source and drain lines in a column containing the cell being addressed, and application of a control gate voltage to a word line connected to the control gates in a row containing the cell being addressed.
FIG. 2 shows schematically an addressable array of non-volatile memory cells 10 with row and column decoding circuits 50, 52 and a read circuit 60.
Referring also to FIG. 1, when the cell 40 is addressed for programming or reading, appropriate programming or reading voltages (VCG, VS, VD) must be supplied respectively to the cell""s control gate 46, source 43 and drain 44. An address is applied to the row decoder 50 for connecting VCG to the word line 30 which in turn is connected to the control gate of the cell 40. The same address is also applied to the column decoder 52 for connecting VS to the source line 20 and VD to the drain line 22, which are respectively connected to the source and drain of the cell 40.
The memory state of the addressed memory cell 40 is read with the read circuit 60 placing the appropriate operating voltages across the cell""s source and drain, and then detecting the level of conduction current flowing between the source and drain.
In the usual two-state EEPROM cell, at least one current breakpoint level is established so as to partition the conduction window into two regions. When a cell is read, its source/drain current is resolved into a memory state by comparing with the breakpoint level (or reference current Iref). If the current read is higher than that of the breakpoint level or Iref, the cell is determined to be in one logical state (e.g., a xe2x80x9czeroxe2x80x9d state), while if the current is less than that of the breakpoint level, the cell is determined to be in the other logical state (e.g., a xe2x80x9conexe2x80x9d state). Thus, such a two-state cell stores one bit of digital information. A reference current source which may be externally programmable is often provided as part of a memory system to generate the breakpoint level current.
When a cell is programmed to a given state, it is subject to successive programming voltage pulses, each time adding incremental charge to the floating gate. In between pulses, the cell is read back or verified to determine its source-drain current relative to the breakpoint level. Programming stops when the current state has been verified to be in a desired region of the partitioned conduction window.
For a multi-state or multi-level EEPROM memory cell, the conduction window is partitioned into more than two regions by more than one breakpoint such that each cell is capable of storing more than one bit of data. The information that a given EEPROM array can store is thus increased with the number of states that each cell can store. EEPROM or flash EEPROM with multi-state or multi-level memory cells have been described in U.S. Pat. No. 5,172,338.
FIG. 3A illustrates a chunk of memory cells 1 to k being read by a bank of sense amplifiers SA1, . . . , SAk, according to the prior art. Each sense amplifier senses the source-drain current of the cell it is connected to. To increase read performance, a plurality of cells is typically read in parallel chunk-by-chunk. Thus, cell 1, 2, . . . , k is respectively read by sense amplifier 1, 2, . . . , k, and the outputs "PHgr"1, "PHgr"2, . . . "PHgr"k are latched in a chunk shift register. When all bits of the chunk are stored in the chunk shift register, the chunk can be shifted out serially. In the example, the conduction window of each cell is partitioned by three breakpoints. Each sense amplifier senses the source-drain current of a cell in the chunk and resolves the current into a memory state by comparing it relative to three reference currents, Iref1, Iref2 and Iref3. Therefore, the three breakpoints can in principle partition the conduction window into four regions representing four possible memory states of the cell.
However, in practice, owing to the noises found in both the sensed current of a cell and the reference currents it is compared to, if the two currents are close together within their error margins, the memory state of the cell cannot be determined definitely. To offset this, a cell is usually programmed well into a partitioned region. In this way, even if the verification or read has an error due to noise, a margin of safety has been programmed to enable the programmed state of the cell to be read correctly. This is accomplished by setting up a margin or a guard band around each breakpoint or reference current. During program verification, the sensed cell current must clear such a margin in order to guarantee that it is programmed well within a desired conduction region of the partitioned window.
FIG. 3B(a) illustrates a reference clock in which a reading may be taken at each clock cycle. FIG. 3B(b) shows an initial setup period for read where the currents are irregular and not ready for read. After this setup period, the currents settle down to a stable and quiescent state and are ready for read (i.e., comparison of the cell""s current against a reference current). FIG. 3B(c) illustrates that if a reading is taken every clock cycle, the sensed cell current typically has a noise fluctuation which may be denoted by xcex94I.
FIG. 3C illustrates the use of breakpoint levels to partition the non-volatile memory""s conduction window into separate regions in order to allow multi-state storage, and the implementation of a guard band around each breakpoint level to allow for noise fluctuations. In the example, the conduction window is from about 1 xcexcA to about 50 xcexcA. Three breakpoints, Iref1, Iref2 and Iref3 (e.g., 6, 20 and 40 xcexcA) partition the source-drain range or window into four regions representing memory states xe2x80x9c3xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d respectively. The reading is done with the control gate voltage set at 5V. The four solid I(t) versus VCG lines represent four possible charge levels that can be programmed on a floating gate of a memory cell, respectively corresponding to four possible memory states. In order to allow for the possible noise fluctuation xcex94I, a margin of xcex94I on either side of the breakpoint is set up when the cell is being programmed. Thus, a cell must be programmed with a charge that gives rise to a sensed current clearing the margins. In this way, when the cell is subsequently read, it will be read correctly even if there is an error of xcex94I associated with noise fluctuations.
As an example, the margin can be xc2x15 xcexcA around each breakpoint, forming a guard band 10 xcexcA wide. With three guard bands, they could take up 60 percent of the current window. Thus, it can be seen that the use of margins or guard bands will substantially consume valuable space in the conduction window ofa memory cell and therefore significantly reduce the number of possible partitions. As a result, floating-gate memory devices in the past have been mostly two-state, and it has been difficult to increase the storage capacity of these devices significantly above two-state.
Accordingly, it is a primary object of the present invention to improve the storing capacity of floating-gate memories where each cell can support memory states substantially greater than two.
It is a further object of the present invention to provide improved read and program circuits as part of an EPROM, EEPROM or flash EEPROM integrated circuit memory chip.
It is also an object of the invention to provide read and program circuits which are simpler, easier to manufacture and have improved accuracy and reliability over an extended period of use.
It is yet another object of the present invention to provide Flash EEPROM semiconductor chips that can replace magnetic disk storage devices in computer systems.
These and additional objects are accomplished by improvements in EEPROM array read and write circuits and techniques where the range of charge programmable into the floating gate of a memory cell gives rise to a corresponding range of conduction states detectable by corresponding cell conduction currents across the source and drain of the cell, and where each resolvable conduction state is usable to represent a logical memory state, the improvement being a sense amplifier and method where the sensing accuracy of the cell current level is substantial improved by averaging the cell current over a predetermined period of time sufficient for noise fluctuations therein to cancel to a predetermined value, and in the process also resolves in the digital domain the noise-canceled current level directly into a memory state.
The improved sensing accuracy allows the range of conduction states (conduction window) of the cell to be finely partitioned to support higher density storage. In this way, it is possible to have two or substantially more distinct states within each memory cell over an extended lifetime of the memory cells, so that one or substantial more bits may be reliably stored in each cell.
A conventional sense amplifier is substantially less accurate because it senses a noisy cell current. The error is further compounded by having to resolve its memory state in the analog domain by comparing against yet another noisy reference current that is used to demarcate the states of the conduction windows. The input noise rejection of instantaneous sensing is low. There is also noise from output switching as well as poor rejection of power line noise. Margins have to be set up in the partitioning of the conduction window to offset the sensing and resolving errors. This prevents finer partitioning of the conduction window, resulting in lower density cell storage.
According to one embodiment of the present invention, the averaging of the cell current is accomplished by a current-to-frequency converter that outputs a wave train with a frequency proportional to the cell current. The converter operates over a predetermined integration time that is long compared to the noise fluctuation of the cell current and outputs a wave train segment in that time. The number of cycles in the wave train segment is counted by a counter and is proportional to the sensed, time-averaged current. A timer circuit provides the timing for the integration time.
In one embodiment of the counter for a n-bit cell, the counter comprises a series of at least n-cascading Divide-By-Two frequency dividers, that in combination output the count in the wave train segment as a memory state in binary format.
In the preferred embodiment, a group (chunk) of cells is sensed in parallel and the sensed states are shifted out by a shift register chunk-by-chunk. In this way, the longer time required to perform a time-averaged sensing for each cell is offset by the time saving when sensing a chunk of cells in parallel.
Thus, the invention provides much more accurate sensing by avoiding the convention methods of sensing cell currents with their noise fluctuations untreated, and avoiding having to determine the relative location of the sensed current in the conduction window by comparing it against another noisy reference current in the analog domain.
According to another embodiment of the invention, adaptation is made to existing sense amplifier architectures where the memory cell current is compared to a reference current. An integrating comparator is employed where the comparison between the two currents are made over the predetermined period of time sufficient for noise fluctuations therein to cancel to a predetermined value. Preferred embodiments of the integrating comparator include symmetric, switched or non-switched capacitor differential amplifier. The resulting advantage is that little modifications need be made to existing highly optimized circuits. In addition, conventional, and well known integrating amplifier techniques or switched capacitor differential amplifier can be employed. By the same token, these techniques are typically used in combination with other well established techniques such as filtering, analog-digital conversion, including offset cancellation and power supply or other noise rejections.
Additional objects, features and advantages of the present invention will be understood from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.